|
Written by achingrover
|
|
Monday, 21 July 2008 13:50 |
|
In this article I would try to cover the basic difference between Transition Fault and Path delay testing and how the current TFT proves inadequate in targeting the transition faults. So, what is TFT? As the name suggests, TFT is to make sure that if we make a transition through a node, it is captured within an intended time period. Since rise and fall time can be different, we assume two types of transition fault can occur viz slow-to-rise and slow-to-fall. Hence a path which fails at at-speed will pass at lower frequencies. Let’s take a simple example in the figure below: |
|
Last Updated ( Monday, 21 July 2008 13:51 )
|
|
Read more...
|
|
|
Written by Nidhi Varshneya
|
|
Friday, 04 July 2008 14:23 |
|
In an industry which is seeing ever shrinking technologies and increasing demand of a complete solution chips, timely and efficient timing closure is becoming a bottleneck. More so at 90nm and below the physical effects and design styles present new challenges for accurate delay calculation. Top-level interconnect is becoming more resistive with narrow metal widths, resulting in cases where the interconnect impedance is much higher than the driving cell. Analysis is needed across a wide range of Vdd values to support dynamic IR drop effects and with the advent of multi-Voltage chips, proper scaling of delay across the voltage domains is required. |
|
Last Updated ( Friday, 04 July 2008 14:34 )
|
|
Read more...
|
|
|
Thursday, 03 July 2008 13:02 |
|
(This article is added after consent from Suresh. You can read more of his articles in http://chipverification.blogspot.com) Even though a lot of STA and Formal verification tools exists in the industry now a days, one question still arises in the mind of many verification engineers. The question is "Why do we go for a gate level simulation?"
Some years ago, I felt that gate level simulation were not worth. In my view, if we do static timing analysis (STA) after post and route, and take the post routed net-list, Extracted Parasitics File and design timing constraints, then perform design timing checks at all corners - say setup, hold and clock gating check - then we should be OK, no need to perform the gate level simulation. Then I realized if our chip has system clocks that only talk to others in synchronous, works in a single mode of operation and the STA setup includes no constants and false paths, then we can cover everything through STA tools.
|
|
Last Updated ( Thursday, 03 July 2008 16:19 )
|
|
Read more...
|
|
|
